Germanium-silicon-carbide floating gates in memories

ABSTRACT

The use of a germanium carbide (GeC), or a germanium silicon carbide (GeSiC) layer as a floating gate material to replace heavily doped polysilicon (poly) in fabricating floating gates in EEPROM and flash memory results in increased tunneling currents and faster erase operations. Forming the floating gate includes depositing germanium-silicon-carbide in various combinations to obtain the desired tunneling current values at the operating voltage of the memory device.

This application is a divisional of U.S. application Ser. No. 11/063,825filed Feb. 23, 2005, which is incorporated herein by reference in itsentirety.

TECHNICAL FIELD

This application relates generally to semiconductor devices and devicefabrication and, more particularly, to transistor gate materials andtheir properties, and in particular to floating gate devices.

BACKGROUND

The electronic device industry uses many different types of memory incomputers and other electronic systems, such as automobiles and trafficcontrol systems. Different types of memory have different access speedsand different cost per stored bit. For example, items of memory thatrequire rapid recovery may be stored in fast static random access memory(RAM). Information that is likely to be retrieved a very short timeafter storage may be stored in less expensive dynamic random accessmemory (DRAM). Large blocks of information may be stored in low cost,but slow access media such as magnetic disk. Each type of memory hasbenefits and drawbacks, for example DRAMs lose the stored information ifthe power is shut off. While the magnetic memory can retain the storedinformation when the power is off (known as non-volatile), the time toretrieve the information is hundreds of times slower than semiconductormemory such as RAM. One type of non-volatile semiconductor memory deviceis electrically programmable read-only memory (EPROM). There are alsoelectrically-erasable programmable read-only memory (EEPROM) devices.One type of EEPROM is erasable in blocks of memory at one time, and isknown as flash memory. Flash memory is non-volatile like magneticmemory, is much faster than magnetic memory like RAM, and is becomingwidely used for storing large amounts of data in computers. However,writing information to a conventional flash memory takes a higher writevoltage than it does to write information to conventional RAM, and theerase operation in flash requires a relatively long time period.

Conventional EEPROM devices, such as flash memory, may operate by eitherstoring electrons on an electrically isolated transistor gate, known asa floating gate, or not storing electrons on the floating gate.Typically the write (or program) operation and the erase operation areperformed by another transistor gate, known as the control gate, whichis located above the floating gate. A large positive voltage on thecontrol gate will draw electrons from the substrate through the gateoxide and trap them on the floating gate. The erase operation uses alarge negative voltage to drive any stored electrons on the floatinggate off of the gate and back into the substrate, thus returning thefloating gate to a zero state. This operation may occur through variousmechanisms, such as Fowler-Nordheim (FN) tunneling. The rate at whichthe electrons can be transported through the insulating gate oxide toand from the floating gate is an exponential factor of both thethickness of the insulator and of the electrical height of theinsulation barrier between the substrate and the floating gate. Growngate oxides have great height, and slow tunneling.

Electronic devices have a market driven need to reduce the size andpower consumption of the devices, such as by replacing unreliablemechanical memory like magnetic disks, with transistor memory likeEEPROM and flash. These increasingly small and reliable memories willlikely be used in products such as personal computers (PCs), personaldigital assistants (PDAs), mobile telephones, laptop PCs, and even inreplacing the slow hard disk drives in full sized computer systems. Thisis because a solid state device, such as flash memory, is faster, morereliable and has lower power consumption than a complex and delicatemechanical system such as a high speed spinning magnetic disk. What isneeded is an improvement in the erase time for EEPROM devices. Withimproved erase times, the high density of flash memory, and a speed ofoperation comparable to DRAMs, flash memory might replace both magneticmemory and DRAMs in certain future computer devices and applications.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a transistor with a germanium silicon carbide gate,according to embodiments of the present subject matter;

FIG. 2 illustrates a non-volatile memory element with a germaniumsilicon carbide gate, according to embodiments of the present subjectmatter;

FIG. 3 is an energy band diagram for a polysilicon gate transistor;

FIG. 4 is an energy band diagram for a silicon carbide gate transistor,according to an embodiment;

FIG. 5 is a diagram showing bandgap versus electron affinity accordingto an embodiment; and

FIG. 6 illustrates a diagram for an embodiment of an electronic systemhaving devices with a floating gate transistor containing a mixture ofgermanium, silicon and carbon according to an embodiment.

DETAILED DESCRIPTION

The following detailed description refers to the accompanying drawingsthat show, by way of illustration, specific aspects and embodiments inwhich the present invention may be practiced. These embodiments aredescribed in sufficient detail to enable those skilled in the art topractice the present invention. Other embodiments may be utilized andstructural, logical, and electrical changes may be made withoutdeparting from the scope of the present invention. The variousembodiments are not necessarily mutually exclusive, as some embodimentscan be combined with one or more other embodiments to form newembodiments.

The terms wafer and substrate used in the following description includeany structure having an exposed surface with which to form an integratedcircuit (IC) structure. The term substrate is understood to includesemiconductor wafers. The term substrate is also used to refer tosemiconductor structures during processing, and may include other layersthat have been fabricated thereupon. Both wafer and substrate includedoped and undoped semiconductors, epitaxial semiconductor layerssupported by a base semiconductor or insulator, as well as othersemiconductor structures well known to one skilled in the art. The termconductor is understood to generally include n-type and p-typesemiconductors and the term insulator or dielectric is defined toinclude any material that is less electrically conductive than thematerials referred to as conductors or as semiconductors.

The term “horizontal” used in this application is defined as a planeparallel to the conventional plane or surface of a wafer or substrate,regardless of the orientation of the wafer or substrate. The term“vertical” refers to a direction perpendicular to the horizontal asdefined above. Prepositions, such as “on”, “side” (as in “sidewall”),“higher”, “lower”, “over” and “under” are defined with respect to theconventional plane or surface being on the top surface of the wafer orsubstrate, regardless of the orientation of the wafer or substrate. Thefollowing detailed description is, therefore, not to be taken in alimiting sense, and the scope of the present invention is defined onlyby the appended claims, along with the full scope of equivalents towhich such claims are entitled.

Field effect transistors (FETs) are used in many different electronicdevices, including memory devices. FETs are used both as accesstransistors and as memory elements. The structure of a typical FET 100is shown in FIG. 1, where a lightly doped substrate 102 has a heavilyoppositely doped source region 104 and drain region 106. The portion ofthe substrate 102 located between the source region 104 and the drainregion 106 is known as the channel region 108, and may have a dopinglevel that is different from the doping level of the substrate 102, andmay even be counter doped to have a doping type opposite of thesubstrate. The substrate may be either lightly doped P type or N type,and the diffused source and drain regions will be heavily doped with theopposite doping type. There is a gate oxide 110 located over the channelregion 108, and making at least some contact with each of the sourceregion 104 and drain region 106. The gate oxide 110 is an insulator,such as thermally grown silicon dioxide, and at normal operatingvoltages prevents current flow from the substrate 102 to a conductivegate electrode 112. Conductive gate electrode 112 is located on top ofthe gate oxide 110, and also extends at least some distance over each ofthe source region 104 and drain region 106. Conventional gate electrodesare formed of doped polycrystalline silicon (poly or polysilicon).Embodiments of the present subject matter form gate electrode 112 with agermanium silicon carbide (GeSiC) composition. In operation, when asignal is directed to the gate 112 over an electrical connection 120,the signal voltage affects the concentration of electrical carriers inthe channel region 108. For example, if a positive voltage having agreater value than what is known as the threshold voltage of thetransistor 100 is applied to gate 112, then the relatively small numberof electrons (negative carriers) in the P type substrate 102 will beattracted to the channel region 108 in great enough numbers to overwhelmthe positive holes in the channel region, and thus temporarily convertthe channel region to be N type as long as the positive voltage isapplied to the gate 112. Thus a large enough positive voltage (known asthe threshold voltage) on the gate 112 will electrically connect thesource region 104 to the drain region 106 and turn on the transistor100. The threshold voltage depends upon the thickness and dielectricconstant of the gate insulator 110, the doping level of the channelregion 108, and the electron affinity of the material forming the gateelectrode 112. Thus, a gate electrode made of a material such as GeSiCmay have the threshold voltage of the transistor adjusted to a desiredlevel by changing the electron affinity of the transistor, and may thusreduce the number and size of ion implantation adjustments of thechannel doping level.

The illustrative floating gate transistor 200, as shown in FIG. 2, mayhave a lightly doped substrate 202 with a heavily oppositely dopedsource region 204 and drain region 206. For example, the substrate 202may be a lightly doped P type region, and the source region 204 anddrain region 206 would then be heavily doped N+ type. The portion of thesubstrate 202 located between the source region 204 and the drain region206 is again known as the channel region 208, and may have a dopinglevel that is different from the doping level of the substrate 202.There is a gate oxide 210 located over the channel region 208, which isan insulator such as thermally grown silicon dioxide. There is anelectrically floating conductive gate 212, located on top of the gateoxide 210, which unlike the previously discussed transistor 100 of FIG.1, has no direct connection to signal voltages, and is typically calleda floating gate since it is electrically floating. Conventionally,floating gates are typically formed of doped polysilicon. Embodiments ofthe present subject matter form floating gate 212 with a germaniumsilicon carbide composition. There is an inter-gate dielectric orinsulator 214 which electrically separates the floating gate 212 from acontrol gate 216, which is also typically made of polysilicon. Inoperation the control gate is connected to signal voltage 220. Thesignal voltage 220 must be larger than the signal voltage 120 for theconventional transistor since the control gate is further from thechannel region 208 and because the electrons in the channel region mustbe at a high enough voltage to be injected through the gate oxide 210 tobecome trapped on floating gate 212. A given signal voltage level willprovide a current of electrons through the gate oxide 210 that dependsexponentially upon the level of the signal voltage, the thickness of thegate oxide 206 and the electrical height of the barrier formed by thegate oxide 210 between the energy levels of the substrate at the channel208 and the energy level of the floating gate 212. Changing the materialof the substrate 202 or of the floating gate 212 changes the electricalheight of the barrier formed by the gate oxide 210, and radicallychanges the amount of current that tunnels through the gate oxide 206 bymeans of Fowler-Nordheim tunneling. Thus, changing the tunneling barrierheight results in erase operations that have larger currents at a givenerase voltage level, and therefore result in faster erase times formemory devices. Another advantage of lowering the tunneling barrierheight is that lower erase voltages may be used. Lower erase voltagesmean lower electrical fields for a given dielectric thickness, andtherefore reduced reliability issues such as time dependent dielectricbreakdown of the gate insulator and inter-gate insulator.

The reason that changing the material of the substrate or of thefloating gate changes the electrical height of the tunneling barrier isbest understood by examination of what is known as an energy banddiagram, as shown in FIG. 3 for the typical memory transistor discussedin FIG. 2 and used in flash memory. As noted above, the excellentquality of grown gate oxides results in a large electrical height of thetunneling barrier formed by the oxide. This high quality oxide resultsin lower programming currents and lower erase currents and causes slowermemory operation. An issue with other gate insulators besides grownoxides, such as chemical vapor deposited (CVD) oxides, silicon nitride,aluminum oxide, tantalum oxide, and titanium oxides, is that the resultshave proven unacceptable from a device electrical performance point ofview, including high levels of what are known as surface states. If thesurface states are reduced by growing a thin oxide underneath thedeposited oxide, then the interface between the two insulators may havelarge numbers of what are known as trap states, and may have band gapdiscontinuities and differences in the conductivity of the insulatorfilms. Thus, changing the gate insulator to reduce the tunneling barrierheight and voltage may pose problems, particularly with maintainingconsistent time-dependent device electrical operation.

Another method of changing the tunneling voltage, and thus equivalentlyincreasing the tunneling current at a particular voltage level, is tochange the overall tunneling barrier height by increasing the internalenergy level of the conductors on either side of the insulator, ratherthan by lowering the insulator barrier level. Changing the siliconsubstrate to some other material may cause numerous practical problemsin the fabrication of devices, since so much is known about the use ofsilicon. Changing the material of the floating gate to a material withwhat is known as a lower electron affinity, denoted by the lower caseGreek letter Chi (χ) results in higher tunneling currents. A lowerelectron affinity reduces the effective height of the insulatortunneling barrier, which as noted previously has an exponential effecton the amount of tunneling current at a given voltage.

A transistor built on a single crystal silicon substrate has a band gapdiagram 300, with a conduction level 302, a valence level 304, and aFermi level 306, as shown for a lightly doped P type silicon substratewith reference to the vacuum level 308, which represents the amount ofenergy it would take to remove an electron from the silicon. On theopposite side of a gate oxide 309, heavily doped N type polycrystallinesilicon will have a conduction level 310, a Fermi level 312 and avalence level 314. The gate oxide 309 has an energy level value 316,whose difference from the vacuum level 308 represents the electronaffinity χ of the gate oxide, typically thermally grown silicon dioxide.For good quality thermally grown silicon dioxide, the value of χ is 0.9eV. For electrons on the floating gate conduction band 310, the value ofelectron affinity χ is the difference between 310 and the vacuum level308, and for doped polysilicon is approximately 4.1 eV. Thus, thebarrier that an electron tunneling from the floating gate 212 conductionband 310 to the silicon substrate 202 in the area of the channel 208,must traverse during an erase operation is the height represented by thedifference between the top of the gate oxide 316 and the conduction band310, or 4.1 eV minus 0.9 eV, or about 3.2 eV. As noted previously, thetunneling rate is an exponential factor of the height of the barrier,and the width of the oxide, which is controlled by the process parameterof gate oxide thickness.

The distance between the conduction level 310 and the valence level 314is known as the band gap, and has a value in silicon of approximately1.1 eV. Since the value of electron affinity for the gate oxide is notgoing to change, then the use of a floating gate material that has alarger band gap would result in a lower electron affinity, and thus areduced tunneling barrier. Changing the electron affinity of the gatematerial also changes the threshold voltage of the transistor, and maybe used in conjunction with channel doping levels and gate insulatorthickness and dielectric constant to adjust the threshold voltage level.

FIG. 4 illustrates the band gap diagram 400 for an embodiment of asilicon carbide gate material. There is still a silicon substrateconduction level 402, a silicon substrate valence level 404, and a Fermilevel 406 with reference to the vacuum level 408. On the opposite sideof the thermally grown silicon dioxide gate oxide 409, the illustrativesilicon carbide gate will have a conduction level 410, a Fermi level 412and a valence level 414, all of which may be different from the valuesin the case of polysilicon gates. The gate oxide 409 still has the sameenergy value 416, and electron affinity χ of the gate oxide, typically0.9 eV. The band gap for silicon carbide depends upon the ratio ofsilicon to carbon, and varies from the silicon value of 1.1, as notedabove, to the pure carbon value of approximately 4.2 eV. For a siliconcarbide mixture, the value of the band gap is about 2.1 eV to 2.6 eVdepending upon the percentage of carbon. Since the conduction band isnow closer to the vacuum level 408, the electron affinity is lower,about 3.7 eV, and the height of the tunneling barrier is now lower,typically below 2.8 eV, which is lower than the tunneling barrier foundin the case of polysilicon of about 3.2 eV. Thus, the tunneling barrieris lowered, and even a small difference in tunneling barrier heightcauses a large change in tunneling current. For germanium carbide, avery similar band diagram shows a tunneling barrier that extends from alarger value than that of polysilicon for a pure germanium gate of 3.6eV, to a barrier value that is the same as the polysilicon value of 3.2eV at a 4% carbon content, to lower values for increased carbon contentabove the 4% level. The values for silicon, silicon carbide andgermanium carbide are discussed in more detail with respect to FIG. 5later in this disclosure. Increased tunneling current flow at a givenerase voltage value results in much faster erase operations and improvedEEPROM or flash memory operational speeds.

Crystalline silicon carbide and silicon germanium carbide can beepitaxially grown on a silicon substrate and may be used in both metaloxide semiconductor field effect transistors (MOSFET) or bipolartransistor devices, with the silicon substrate acting as a seed layerfor crystal growth. In an embodiment the silicon carbide, germaniumcarbide and silicon germanium carbide are microcrystalline or amorphous.Such microcrystalline layers or amorphous layers may be grown oninsulator layers such as silicon dioxide gate insulator layers, or otherinsulator layers, by chemical vapor deposition (CVD), laser assistedCVD, plasma CVD, ultra-high vacuum CVD, or sputtering.

FIG. 5 is a graph 500 that illustrates the ability to adjust thetunneling barrier height, and thus the tunneling barrier current level,for various embodiments of mixtures of silicon 504, germanium 506, andcarbon in the form of diamond 508. The values of germanium carbide ofvarying percentages of germanium are shown by the line connecting 506and 508, including the interesting point 510 where a 4% carbon value ingermanium provides the same band gap 1.1 eV as pure silicon 504, butwith a lower electron affinity χ and thus improved tunneling currentsand faster erase operations without other significant electrical changesin the transistor operation due to changes in the band gap value.Silicon carbide values are projected on the line from 504 to 508, withsilicon carbide having a band gap with a 2.1 eV value shown at 512.Various embodiments of the present disclosed methods and devices can befound in the region of the graph between 510 and 512 and the entire areabetween the lines representing germanium carbide and silicon carbidecompositions. An illustrative silicon germanium carbide material withequal amounts of silicon and germanium and varying amounts of carbonwould have a band gap to electron affinity χ curve that fits abouthalfway between the germanium carbide line and the silicon carbide line.

FIG. 6 depicts a diagram of an embodiment of a system 600 having acontroller 602 and a memory 606. Controller 602 and/or memory 606include a transistor having a gate electrode made of a mixture ofgermanium, silicon and carbon. System 600 also includes an electronicapparatus 608, and a bus 604, where bus 604 may provide electricalconductivity and data transmission between controller 602 and electronicapparatus 608, and between controller 602 and memory 606. Bus 604 mayinclude an address, a data bus, and a control bus, each independentlyconfigured. Bus 604 also uses common conductive lines for providingaddress, data, and/or control, the use of which may be regulated bycontroller 602. In an embodiment, electronic apparatus 608 includesadditional memory devices configured similarly to memory 606. Electronicapparatus 608 may include, but is not limited to, information handlingdevices, wireless systems, telecommunication systems, fiber opticsystems, electro-optic systems, and computers. An embodiment includes anadditional peripheral device or devices 610 coupled to bus 604. In anembodiment controller 602 is a processor. Any of controller 602, memory606, bus 604, electronic apparatus 608, and peripheral device or devices610 may include a gate electrode formed of a mixture of silicon,germanium and carbon in accordance with the disclosed embodiments.

System 600 may include, but is not limited to, information handlingdevices, telecommunication systems, and computers. Peripheral devices610 may include displays, additional storage memory, or other controldevices that may operate in conjunction with controller 602 and/ormemory 606. It will be understood that embodiments are equallyapplicable to any size and type of memory circuit and are not intendedto be limited to a particular type of memory device.

CONCLUSION

An embodiment has a floating gate transistor with a gate made of amaterial having a lower tunneling barrier and thus lower erase times.Another embodiment has the floating gate formed of germanium siliconcarbide. Another embodiment has the composition of the floating gatedetermined by a desired tunneling current. Another embodiment includes atransistor with a conventional gate having the composition of thegermanium silicon carbide adjusted to optimize the threshold of a metaloxide semiconductor field effect transistor (MOSFET).

An embodiment for a method for forming a floating gate memory deviceincludes forming a floating gate having a lower tunneling barrier byforming the gate of a mixture of germanium, silicon and carbon. Anotherembodiment includes a method of storing data by setting the voltage ofthe control gate, drain diffusion and source diffusion to either trapelectrons on a floating gate made of germanium, silicon and carbon, orby ejecting trapped electrons from the floating gate by Fowler-Nordheimtunneling.

Applications include structures for transistors, memory devices such asflash, and electronic systems with gates containing a mixture ofgermanium, silicon and carbon, and methods for forming such structures.

Although specific embodiments have been illustrated and describedherein, it will be appreciated by those of ordinary skill in the artthat any arrangement that is calculated to achieve the same purpose maybe substituted for the specific embodiments shown. It is to beunderstood that the above description is intended to be illustrative,and not restrictive, and that the phraseology or terminology employedherein is for the purpose of description and not of limitation.Combinations of the above embodiments and other embodiments will beapparent to those of skill in the art upon studying the abovedescription. The scope of the embodiments of the present inventionshould be determined with reference to the appended claims, along withthe full scope of equivalents to which such claims are entitled.

1. A method of storing data in a memory device, comprising: addressingselected ones of a plurality of memory cells with selected ones of aplurality of word lines and a plurality of bit lines; increasing avoltage applied to a control gate on the selected memory cells, thememory cells each including a substrate, a source region, a drain regionand a floating gate disposed beneath the control gate and separatedtherefrom by an inter-gate insulator layer, the floating gate comprisinga conductive film including a mixture of germanium, silicon and carbon;trapping electrons on the floating gate in response to a positivevoltage having at least a first voltage level being applied to thecontrol gate for at least a first time period, changing the memory cellto a first memory state; and ejecting electrons from the floating gatein response to a negative voltage having at least a second voltage levelbeing applied to the control gate for at least a second time period,changing the memory cell to a second memory state.
 2. The method ofstoring data in a memory device of claim 1, wherein further the floatinggate comprises a mixture having a lower electron affinity than a dopedpolycrystalline silicon floating gate.
 3. The method of storing data ina memory device of claim 1, wherein the floating gate composition isselected to obtain a desired tunneling current value for ejectingelectrons from the floating gate during the second time period when thenegative second voltage level is applied to the control gate.
 4. Themethod of storing data in a memory device of claim 1, wherein the memorydevice is controlled as a flash memory.
 5. The method of storing data ina memory device of claim 1, wherein the floating gate has a structurethat is one of micro-crystalline and amorphous.
 6. The method of storingdata in a memory device of claim 1, further comprising a programmingvoltage signal of approximately 12 volts on the control gate for thefirst time period, a voltage level of approximately 6 volts on the drainregion for at least the first time period, a voltage level of a groundon the source region for at least the first time period, and electronsfrom the substrate trapped on the gate electrode.
 7. The method ofstoring data in a memory device of claim 1, further comprising an erasesignal of approximately negative 12 volts on the control gate for thesecond time period, a voltage level of ground on the source region forat least the second time period, and electrons ejected from the gateelectrode to the substrate.
 8. A method of storing data in a memorydevice having a source region and a drain region separated by a channelregion in a substrate, a gate insulator adjacent to the channel region,a floating gate on the gate insulator comprising a conductive filmincluding germanium, silicon and carbon, an inter-gate insulator on thefloating gate, a control gate on the inter-gate insulator, comprising:trapping electrons on the floating gate in response to a positivevoltage having a first voltage level applied to the control gate for afirst time period, changing the memory cell to a first memory state; andejecting electrons from the floating gate in response to a negativevoltage having a second voltage level applied to the control gate for asecond time period, changing the memory cell to a second memory state.9. The method of storing data in a memory device of claim 8, whereintrapping electrons on the floating gate includes selecting proportionsof germanium, silicon and carbon to obtain a material having a lowerelectron affinity than a polycrystalline silicon floating gate.
 10. Themethod of storing data in a memory device of claim 9, wherein trappingelectrons on the floating gate includes selecting proportions ofgermanium, silicon and carbon to obtain a desired tunneling currentvalue for ejecting electrons from the floating gate.
 11. The method ofstoring data in a memory device of claim 8, wherein storing data furtherincludes a programming voltage signal of 12 volts on the control gate, avoltage level of 6 volts on the drain region, a voltage level of areference voltage on the source region, resulting in electrons from thesubstrate becoming trapped on the floating gate.
 12. The method ofstoring data in a memory device of claim 11, wherein storing datafurther includes maintaining each of the programming voltage signal, thedrain voltage level and the source reference voltage level, for at leasta desired first time period.
 13. The method of storing data in a memorydevice of claim 11, wherein storing data further includes setting thereference voltage level to a ground voltage level.
 14. The method ofstoring data in a memory device of claim 8, wherein storing data furtherincludes an erase voltage signal of negative 12 volts on the controlgate, a voltage level of a reference voltage on the source region,resulting in electrons trapped on the floating gate being ejected to oneof the substrate and the drain region.
 15. The method of storing data ina memory device of claim 11, wherein storing data further includesmaintaining each of the erase voltage signal and the source referencevoltage level, for at least a desired second time period.
 16. The methodof storing data in a memory device of claim 8, wherein trappingelectrons on the floating gate further includes a percentage ofgermanium about 96%, a percentage of silicon about 0%, and a percentageof carbon about 4%, forming germanium carbide having a band gap ofapproximately 1.1 eV.
 17. The method of storing data in a memory deviceof claim 8, wherein trapping electrons on the floating gate furtherincludes a percentage of germanium about 25%, a percentage of siliconabout 25%, and a percentage of carbon about 50%, forming germaniumsilicon carbide having a band gap of approximately 2.5 eV.
 18. Themethod of storing data in a memory device of claim 8, wherein trappingelectrons on the floating gate further includes selecting a percentageof germanium, silicon and carbon to form a germanium-silicon carbidehaving a band gap greater than 1.1 eV and an electron affinity less than3.5 eV.
 19. The method of storing data in a memory device of claim 8,wherein trapping electrons on the floating gate further includes thefloating gate having no direct electrical connection to either of thesubstrate and the control gate.
 20. The method of storing data in amemory device of claim 8, wherein trapping electrons on the floatinggate further includes the floating gate having at least enoughelectrical conductivity to redistribute trapped electrons essentiallyevenly throughout the film in a time period less than a minimum timeperiod between one of a program and an erase signal, and a next one of aprogram and an erase signal.
 21. The method of storing data in a memorydevice of claim 8, wherein trapping electrons on the floating gatefurther includes a percentage of germanium of zero, a percentage ofsilicon of 50%, and a percentage of carbon of 50%, forming siliconcarbide.
 22. The method of storing data in a memory device of claim 8,wherein trapping electrons on floating gate further includes apercentage of germanium of 50%, a percentage of silicon of zero, and apercentage of carbon of 50%, forming germanium carbide.